2 megabit cmos sram ft s256s8n description: the ft s256s8n is a military 256k x 8 high-density, low-power static ram module comprised of two ceramic 128k x 8 monolithic sram?s, an advanced high-speed cmos decoder and decoupling capacitors surface mounted on a co-fired ceramic substrate having side-brazed leads. the ft s256s8n is available in a 600-mil-wide, 32-pin dual-in-line package that conforms to the same jedec standard pin configuration as the future four megabit monolithics. the ft s256s8n operates from a single +5v supply and all input and output pins are completely ttl-compatible. the low standby power of the ft s256s8n make it ideal for battery-backed applications. features: 262,144 by 8 bit configuration access times: 85*, 100, 120, 150ns - faster speeds upon request low power dissipation: 40 m w (typ.) standby 375 mw (typ.) operating 2-volt data retention fully static operation - no clock or refresh required all inputs and outputs are ttl-compatible 600 mil, 32-pin jedec standard dip pinout * commercial only. pin-out diagram functional block diagram this document contains information on a product that is currently released to production at f o r ce t e ch n olo gi es . f o rc e reserves th e ri gh t to change products or specifications herein without prior notice. 1 f o rc e t ec hn olo gi e s n.c. no connect a0 - a17 address inputs i/o0 - i/o7 data in/out ce chip enable we write enable oe output enable v dd power (+5v) v ss ground pin names
ft s256s8n f o r ce technologies dc output characteristics symbol parameter conditions min. max. unit v oh high voltage i oh = -1.0ma 2.4 - v v ol low voltage i ol = 2.1ma 0.4 v absolute maximum ratings 3 symbol parameter max. unit t stc storage temperature -65 to +150 c t bias temperature under bias -55 to +125 c v dd supply voltage 1 -0.5 to + 7.0 v v i/o input/output voltage 1 -0.5 to v dd +0.5 v truth table mode ce we oe i/o pin supply current not selected h x x high-z standby not selected x x x high-z standby d out disable l h h high-z active read l h l d out active write l l x d in active h = high l = low x = don?t care capacitance 4 : t a = 25 c, f = 1.0mhz symbol parameter max. unit condition c adr address input 35 pf v in = 0v c ce chip enable 20 c we write enable 30 c oe output enable 30 c i/o data input/output 35 dc operating characteristics: over operating ranges symbol characteristics test conditions typ. c i m/b unit min. max. min. max. min. max. i in input leakage current v in = 0v to v dd - -10 +10 -10 +10 -10 +10 m a i out output leakage current v i/o = 0v to v dd , ce or oe = v ih , or we = v il - -10 +10 -10 +10 -10 +10 m a i cc1 active supply current ce = v il , v in = v ih or v il , i out = 0ma 30 50 50 60 ma i cc2 operating supply current cycle = min., duty = 100%, i out = 0ma 75 110 110 120 ma i sb1 full standby supply current v in 3 v dd -0.2v or v in v ss +0.2v, ce 3 v dd -0.2v 8 200 400 1000 m a i sb2 standby current ce = v ih , v in = v ih or v in 3 6 6 6 ma v ol output low voltage i out = 2.1ma - 0.4 0.4 0.4 v v oh output high voltage i out = -1.0ma - 2.4 2.4 2.4 v * typical measurements made at +25 o c, cycle = min., v dd = 5.0v. recommended operating range 1 symbol characteristic min. typ. max. unit v dd supply voltage 4.5 5.0 5.5 v v ih input high voltage 2.2 v dd +0.3 v v il input low voltage -0.5 2 0.8 v t a operating temperature c 0 +25 +70 c i -40 +25 +85 m/b -55 +25 +125 2
f o rc e t ec hn ol og i es ft s256s8n output load load c l parameters measured 1 100pf except t clz , t olz , t chz , t ohz , t whz , and t wlz 2 5pf t clz , t olz , t chz , t ohz , t whz , and t wlz ac test conditions input pulse levels 0v to 3.0v input pulse rise and fall times 5ns * input and output timing reference levels 1.5v * transition measured between 0.8v and 2.2v. ac operating conditions and characteristics - read cycle: over operating ranges no. symbol parameter 85ns 100ns 120ns 150ns unit min. max. min. max. min. max. min. max. 1 t rc read cycle time 85 100 120 150 ns 2 t aa address access time 85 100 120 150 ns 3 t co chip enable to output valid 85 100 120 150 ns 4 t ov output enable to output valid 40 45 50 60 ns 5 t oh output hold from address change 10 10 10 10 ns 6 t clz chip enable to output in low-z 4, 6 5 5 10 10 ns 7 t olz output enable to output in low-z 4, 6 0 0 0 0 ns 8 t chz chip enable to output in high-z 4, 6 45 45 50 60 ns 9 t ohz output enable to output in high-z 4, 6 30 30 35 45 ns ac operating conditions and characteristics - write cycle: over operating ranges 7 no. symbol parameter 85ns 100ns 120ns 150ns unit min. max. min. max. min. max. min. max. 10 t wc write cycle time 85 100 120 150 ns 11 t aw address valid to end of write 80 90 105 115 ns 12 t cw chip enable to end of write 80 90 105 115 ns 13 t dw data to write time overlap 35 35 40 50 ns 14 t dh data hold time from write time 0 0 0 0 ns 15 t wp write pulse width 55 65 75 85 ns 16 t as address set-up time *** 0 0 0 0 ns 17 t ah address hold time 5 5 5 5 ns 18 t whz write enable to output in high-z 4, 6 30 30 35 40 ns 19 t wlz write enable to output in low-z 4, 6 5 5 5 5 ns *** valid for both read and write cycles. data retention characteristics symbol parameter test conditions typ. ( ? ) c i m/b unit min. max. min. max. min. max. v dr data retention voltage ce 3 v dr -0.2v - 2.0 5.5 2.0 5.5 2.0 5.5 v i ccdr2 data retention supply current v dr = 2.0v 4 90 170 700 m a i ccdr3 data retention supply current v dr = 3.0v 4 100 200 800 m a t cdr chip disable to data retention time - 0 0 0 ns t r recovery time t rc = read cycle timing 5 5 5 ms ? typical measurement made at +25 o c, cycle = min., v dd = 5.0v. figure 1. output load ** including probe and jig capacitance. +5v 990 w 1.8k w c l ** d out 3
read cycle 2: ce controlled. we is high. address ce oe data i/o read cycle 1: address controlled. we is high. ce and oe are low. address data i/o data retention waveform ce v dr 2.2v v ss v dd 4.5v 4 ft s256s8n f o r ce t ec hn olo gi es
write cycle 2: ce controlled. oe is high. address ce we data i/o waveform key data valid transition from transition from data undefined high to low low to high or don?t care write cycle 1 : we controlled. oe is low. address ce we data i/o 5 f o rc e t ec hn ol og i es ft s256s8n
notes: 1. all voltages are with respect to v ss . 2. -2.0v min. for pulse width less than 20ns (v il min. = -0.5v at dc level). 3. stresses greater than those under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other co nditions above those indicated in the operational sections of this specification is not implied. exposure to absolu te maximum rating conditions for extended periods may affect reliability. 4. this parameter is guaranteed and not 100% tested. 5. transition is measured at the point of 500mv from steady state voltage. 6. when oe and ce are low and we is high, i/o pins are in the output state, and input signals of opposite phase to the outputs must not be applied. 7. the outputs are in a high impedance state when we is low. mechanical drawing ordering information 6 ft s256s8n f o r ce t ec hn olo gi es
ashley crt, henley, marlborough, wilts, sn8 3rh uk tel: +44(0)1264 731200 fax:+44(0)1264 731444 e-mail info@forcetechnologies.co.uk tech@forcetechnologies.co.uk sales@forcetechnologies.co.uk www.forcetechnologies.co.uk life support applications force technologies products are not designed for use in life support appliances, devices or systems where malfunction of a force technologies product can reasonably be expected to result in a personal injury. force technologies customers using or selling force technologies products for use in such applications do so at their own risk and agree to fully indemnify force technologies for any damages resulting from such improper use or sale. products, and makes no representation or warranties that that these products are free from patent, copyright or mask work infringement, unless all trademarks acknowledged copyright force technologies ltd 200 5 unless otherwise stated in this scd/data sheet, force technologies ltd reserve the right to make changes, without notice, in the products, includ -ing circuits, cells and/or software, described or contained herein in order to improve design and/or performance. force technologies resumes no responsibility or liability for the use of any of these products, conveys no licence or any title under patent, copyright, or mask work to these products, and makes no representation or warranties that that these products are free f rom patent, copyright or mask work infringement, unless otherwise specified.
|
